Electrical computing system for simultaneously performing a plurality of operations on two or more operands

ABSTRACT

A system for performing high speed operations on two operands comprises a first series of filters, one of which corresponds to each of the possible input operands and a second series of filters also including one corresponding to each possible operand of the system. The first and second series of filters are selectively actuated by a first and second source, respectively, such that when the sources are actuated by the user to provide signals corresponding to the desired first and second operands, only the filters of the first and second series corresponding to the selected operands are actuated. A signal applied to an input terminal of the filters will be applied to output terminals thereof only when a filter has been actuated by a signal from a corresponding source. In a system with n filters in each of the series, n2 correlation circuits are provided, each including a pair of input terminals, one of which is coupled to a unique filter of the first series of filters, the other of which is coupled to a unique filter of the second series such that each filter of the first set is coupled to a correlation circuit coupled to a unique filter of the second set to provide an output signal from a correlation circuit which is applied to a display or output device for simultaneously providing signals representing the operations of addition, subtraction, multiplication and division or other operations of the selected operands.

United States Patent 1 1 [111 3,875,392

Keeler, II Apr. 1, 1975 1 ELECTRICAL COMPUTING SYSTEM FOR 1571 ABSTRACTSIMULTANEOUSLY PERFORMING A PLURALITY OF OPERATIONS ON TWO OR MOREOPERANDS [761 lnventor: Miner-S. Keeler, II, 2525 Indian Trl., SE, GrandRapids, Mich. 49506 [22] Filed: June 18, 1973 [21] Appl. No.: 371,258

OTHER PUBLICATIONS J. Earle et al., Exponent Differences & Preshifter,"IBM Tech. Disclosure Bulletin, Dec. 1966, pp. 848-849.

Primary ExaminerMalcolm A. Morrison Assistant Exumt'nerDavid H. MalzahnAttorney, Agent, or FirmPrice, Heneveld, Huizenga & Cooper so. so 25mmaea NUMBER a+ l0.|.0l (omit o 72 E g Q10! 53 52 m as A system forperforming high speed operations on two operands comprises a firstseries of filters, one of which corresponds to each of the possibleinput operands and a second series of filters also including onecorresponding to each possible operand of the system. The first andsecond series of filters are selectively actuated by a first and secondsource, respectively, such that when the sources are actuated by theuser to provide signals corresponding to the desired first and secondoperands, only the filters of the first and second series correspondingto the selected operands are actuated. A signal applied to an inputterminal of the filters will be applied to output terminals thereof onlywhen a filter has been actuated by a signal from a corresponding source.In a system with n filters in each of the series, n correlation circuitsare provided, each including a pair of input terminals, one of which iscoupled to a unique filter of the first series of filters, the other ofwhich is coupled to a unique filter of the second series such that eachfilter of the first set is coupled to a correlation circuit coupled to aunique filter of the second set to provide an output signal from acorrelation circuit which is applied to a display or output device forsimultaneously providing signals representing the operations ofaddition, subtraction, multiplication and division or other operationsof the selected operands.

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SHLU 1 GF 4 J i PROVIDING IDENTIFYING CORRELATING IDENTIFYING OPERANDSOPERANDS OPERANDS OPERANDS I I IO I2 I6 l4 ORDERING [8/ OUTPUTINFORMATION 7 UTILIZING 2o ORDERED FIG I INFORMATION 9| FIG 6 4o LKEYBOARD STORAGE NUMBER 4 33 [3-34 CIRCUIT OURCE S i 35 3e 39 a ISTORAGE NUMBER cIRcuIT SOURCE 2 2" OPERATOR FIG 3 PATENTEB APR 1 9 SHEET2 m g NUMBER SOURCE (0-7 NUMBER SOURCE (0-7) FILTER (0) 4 56 9 Tfmwvwkmwfm l r l m l 4 A M w w n 4 5 6 7 8 m m m m w 3 6 7 8 l m m m w w6 a w 4 R M R 81R 0 m 0 M 2 A: A A ma L. 2 2 E E R 0 MR R R w 8/ 0 O0 0O k 0 2 CF 4r CF 9 CF 7 W 5 l 3 8 fix 8 ix )23 4 5 6 7 8 O 54 7 7 77 7 7R( 5 6 4 8 9 EDnk. 4 4 7 4. BE 4 5 6 5 M U 5 5 5 .H \I \II NF u my a} 3w) w w 7 3 5 8 9 FIG 2A ELECTRICAL COMPUTING SYSTEM FOR SIMULTANEOUSLYPERFORMING A PLURALITY OF OPERATIONS ON TWO OR MORE OPERANDS BACKGROUNDOF THE INVENTION The present invention relates to an improved computingsystem and method and more particularly. to a system for simultaneouslyperforming a plurality of operations on two or more operands.

Much of the time consumed in computer operation is the time consumed inthe arithmetic operations within the computer. With serial arithmeticunits. any operation upon two words (operands) requires a minimum of afull word time since one word must be serially shifted through thearithmetic unit. In parallel arithmetic units which are somewhat faster,some operations may be performed in a simple bit-time such as theaddition of two words since the word may be shifted into the arithmeticunit in a single-bit time. When, however. different operations are to beperformed on the same operators. the step must be repeated for eachoperation thereby greatly increasing the computation time.

Recently. efforts have been made to reduce the computation time byproviding simultaneous computations such as multiply-add andmultiply-subtract units. US. Pat. No. 3,202,805 to L. D. Amdahll. issuedon Aug. 24. I965. represents one such development. Although such asystem generally represents an improvement over the series arithmeticunits. the system still requires several shift registers which increasethe computation time of the system. as well as many components toprovide additional simultaneous computation.

SUMMARY OF THE INVENTION The system of the present invention. however,dis cards conventional techniques employed for providing arithmeticoperations between operands and employs a unique filter system foruniquely identifying selected operands and for providing simultaneousoutput signals representative of the various operations performedbetween the two operands. The computation time is greatly reduced sincethe time required is only the actuation of the filters which can besimultaneous. In one embodiment. this is followed by the actuation of acircuit unique to the two selected operands.

The method employed in providing output signals representative oftheoperands performed on two operands includes the steps of uniquelyidentifying each operand and actuating a circuit unique to the operandswhich actuates an output device representing the results or solution ofthe operations simultaneously performed between the operands.

Systems embodying the present invention include means for providingsignals representing at least first and second operands. A first seriesof filters uniquely identifying each operand of the system is providedand is responsive to the application of signals from the providing meansfor developing an output signal uniquely identifying the operandidentified by the signal. Additional filters are provided to uniquelyidentify each operand of the system and are coupled to the providingmeans. Circuit means are provided for interconnecting the first andadditional filters such that when two signals identifying at least twooperands are applied to the system. a unique pair of interconnectedfilters are actuated. Output means are coupled to each unique pair offilters to simultaneously provide programmed output informationcorresponding to one or more operations performed on the operands.

An object of the present invention is to provide a calculation methodcapable of providing simultaneous outputs representing one or moreoperations per formed on at least two operands.

Another object of the present invention is to provide a high speedcalculating system.

A further object of the present invention is to provide a calculationcircuit employing a first and a second series of interconnected numberfilters. each filter of which corresponds to a unique number.

Still a further object of the present invention is to provide anelectrical circuit for simultaneously providing a plurality of outputsignals representing the results of a plurality of simultaneouscalculations performed between two operands.

These and other objects of the present invention will become apparentupon reading the following description thereof together with theaccompanying drawings in which:

BRIEF DESCRIPTION OF THE DRAWINGS FIG. I is a flow diagram in block formshowing the calculation steps performed in practicing the presentinvention;

FIG. 2A is an electrical circuit diagram in block form, of a portion ofone embodiment of the present invention;

FIG. 2B is an electrical circuit diagram in schematic form of thedisplay portion of the embodiment of FIG. 2A and electricallyinterconnected to the circuit of FIG. 2A by interconnections XX;

FIG. 3 is an electrical circuit diagram in block form of one circuitwhich can be employed to generate signals representing first and secondoperands on which an operation is to be performed;

FIG. 4 is an electrical circuit diagram in schematic form illustratingone embodiment of a number source used in the present invention;

FIG. 5 is an electrical circuit diagram in schematic form illustratingone embodiment of a number filter employed in the present invention;

FIG. 6 is an electrical circuit diagram in block form of one embodimentof a correlator circuit employed in the present invention; and

FIG. 7 is an electrical circuit diagram in schematic and block formillustrating an alternative embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIG.I, it is seen that the computation system embodying the inventionincludes the step 10 of providing signals representing first and secondoperands and providing first and second operand identification units I2and 14 identifying each of the operands. Next, the signals arecorrelated I6 to uniquely identify both of the operands and correlationinformation is processed I8 during which the output inform ation isordered to provide an output signal. The output information is thenapplied to and utilized by a utilization means 20.

The calculating system embodying the present invention is shown indetail in the remaining figures. Before discussing the structure indetail. however. it is noted that providing step 10 may include. forexample. an

electrical keyboard providing signals representative of a number. whichsignals can be of any desired format such as binary. binary codeddecimal or the like. These signals then actuate number sources providingsignals directly used in the present system. The operand identificationprocess steps 12 and I4 include number filters which receive thesimultaneously provided number signals and concurrently uniquelyidentify each of the numbers. This information is correlated by circuitmeans which activate output means in a format suitable for either directdisplay such as an optical display of the resultant number or in aformat which can be used to interface with further processing or controlcircuits such as electrical output signals.

Although the preferred embodiment described herein relates specificallyto numerical calculations of the above discussed arithmetic functions.it is to be understood that the use of the method and system of thepresent invention is not so limited and can be employed. for example, toprovide any of a desired number of operations simultaneously on two ormore operands. For example. the system can be programmed to provide aTaylor or Fourier series expansion of the operands or La Place. or othertransformations.

Continuing now with the description of the preferred embodiment of thesystem. reference is first had to FIGS. 2-6. In FIG. 2, first and secondsources of operators 30 and 32. respectively. generate 3-bit digitalsignals. each bit having a logic l or a logic *O state which can berepresented by a -ll-V electrical signal or a electrical signalrespectively. In the illustrated embodiment. the sources generate uniquesignals for the digits -7 using a number source ofthe type shown in FIG.4. It is understood that the 3-bit binary number sources illustrate oneaspect of the present invention. it being understood that the number ofbits or the coding scheme can be changed. respectively. as necessary toprovide a system of any degree of complexity required for a givenapplication.

The number source shown in FIG. 4 includes three output lines 31. 33 and35 selectively coupled to voltage sources +V and l+-V by three polesingle throw push button switches to provide output logic signals forthe 3-bit code employed. For the number 2. for example. switch 2 will beactuated to close its contacts to provide a logic output signal of 010.When the switch for number 3 is actuated. it will provide a logic outputsignal of (Jl l. The switch representation ofthe number source 30. shownin FIG. 4. is for purposes of illustration only. it being understoodthat the mechanical switches shown will in practice be solid statedevices such as transistors.

In practice it may be desired to provide a single keyboard which a usercan employ to generate electrical signals representing the operands usedby the system. An electrical circuit which can be used together with aconventional digital keyboard is shown in FIG. 3 where a keyboard 36provides digital information to first and second storage circuits 38 and39. respectively. for storing first and second signals. respectively.representative of desired operands.

To simultaneously store the first and second operand signals. a key 34is provided on the keyboard and is actuated after the first operand hasbeen entered on the keyboard to provide a second operand enable signalon conductor 41 which is applied to the storage circuits 38 and 39 toinactivate and activate these circuits respectively. It is noted herethat circuits 38 and 39 can be of conventional design as. for example. ashift register which has enabling and disabling input terminals coupledto conductor 41 such that they will either receive and store informationfrom the keyboard output terminal 40 or the information stored in thecircuit will not be changed by the information on terminal 40.

In use. the operator of the keyboard will first type in the firstoperand which will be stored in circuit 38, then actuate key 34 todisable circuit 38 and activate storage circuit 39 which receives thesubsequently inserted operand signal from output terminal 40 0f thekeyboard. Storage circuits 38 and 39 are coupled to first and secondnumber sources 30 and 32, respectively. such that once the two operandsare inserted into the storage circuit and the keyboard operator actuatesa clear or readout key of the keyboard, the information stored in thestorage circuits is applied to number sources 30 and 32 which respondthereto to generate the 3-bit binary code information and apply it tothe circuit shown in FIG. 2.

It is to be understood that any number of circuit systems will operatetogether with a conventional digital keyboard to provide the desiredactuation of the number sources 30 and 32 employed with the calculatingsystem. The circuit format shown in FIG. 3 is merely illustrative of onesuch system. The actuation of sources 30 and 32 by BCD or other signalsfrom circuit 38 and 39 is conventional and not discussed in detail.

The calculating system shown in FIG. 2 immediately responds to thesignals from the sources and representing the two operands to provide anoutput simultaneously displaying addition. subtraction. multiplicationand division of the two numbers entered in the keyboard by the user ofthe system. The system includes a first series of number filters (i.e..detector or gate circuits) 42-49 corresponding to the numbers 0-7. In asystem where n represents the number of operands in the system. therewill be It number filters in the first series. The number filtersinclude control input terminals 52-59. as seen in the figure. and signalinput terminals 62-69 as also seen in the figure. Each of the controlinput terminals 52-59 is coupled to the output terminal 30' of numbersource 30 to receive therefrom a 3-bit binary coded signalrepresentative of a unique operand generated by the number source. Thus.the interconnecting conductors will include at least three linescoupling terminal 30 to each of the number filters of the first seriesthereof. The signal input terminals 62-69 are each coupled to a supplyvoltage as seen in the figure.

In the embodiment shown in FIG. 2. for the sake of clarity. the circuitelements are shown for performing the operations of addition.subtraction. multiplication and division on the numbers 2 and 3. Thus.the detailed circuit elements for providing only this operation areshown. The number filters of the first of the first series includeoutput terminals 72-79. as seen in the figure. for providing an outputsignal at one of these terminals only when the electrical signal fromterminal 30' ofthe number source uniquely identifies and corresponds tothe number represented by the particular associated number filter. Thus.the number filters in effect couple the signal applied to inputterminals 62-69 to output terminals 72-79 only when actuated by a signalfrom number source 30 which corresponds to that associated numberfilter. When an operand is entered into the systern and actuates numbersource 30. one and only one of the number filters will provide an outputsignal at its associated output terminal.

For the number 2. selected as the first operand of the example. adigital signal UIU. as shown in parentheses adjacent terminal 30. willbe applied to all of the number filters simultaneously but only numberfilter 44 will provide a positive output signal (logic I at outputterminal 74. The remaining number filter outputs will be at a logic low(0) level. Each output terminal of each number filter will in turn becoupled to a plurality of correlator circuits. one for each uniqueoperator of the series. Thus. for number filter 44. output terminal 74will be coupled to eight correlator circuits correspond ing to thecombined operands -27 in the system. In the figure. terminal 74 ofnumber filter 44 is coupled to input terminals til. 83 and 85 ofcorrelators 8U. 82 and 84 for the operations of 22. 2'3 and 24respectively. Each of the correlators further includes an additionalinput control terminal (shown as 86. 87 and 88 for correlators 8U. 82and 84 respectively) to receive a control signal from the outputterminals of a second series of number filters 92-99. Before continuingwith a description of the system. a brief description of one embodimentof the number filters is shown in FIG. 5

and now described.

Basically. the purpose of a number filter is to provide an output signalat an output terminal thereof only when actuated by an electrical signalcorresponding to an operand uniquely identified by the particular number filter. Thus. the filter operates to detect a unique operand. Thus.for number filter 44. shown in FIG. 5. a positive signal will begenerated at output terminal 74 thereofonly when the input terminals64a. 64b and 64c receive a logic (I. logic l and logic 0 signalrespectively. In the embodiment shown in FIG. 5, the number filter canbe comprised of a series of interconnected PNP and NPN transistorshaving their emitter to collector current paths coupled in series. asshown. with their base terminals individually coupled to the three inputconductors to receive the logic drive signals from the number source.Circuit 44. for example. includes a first PNP transistor 140 having anemitter terminal 141 coupled to the 13+ terminal 42. a base terminal I42coupled to input terminal 64a. and a collector terminal 143 coupled tothe emitter terminal of a second transistor 146. Biasing resistors 1-Hand I45 are provided to render the transistor nonconductive upon thereceipt of any signal other than a logic I) and be switched to a conductive state upon the receipt of a logic 0 signal to base terminal I42.Similarly. bias resistor 147 is provided to bias NPN transistor I46 in anonconductive state unless a logic 1 is received and resistors I48 andI49 coupled as shown in the figure to bias PNP transistor 150 in anonconductive state except upon the receipt of a logic U signal appliedto the base terminal thereof by input terminal 641*.

In place of the circuit elements shown. any suitable controlledswitching devices. preferably solid state. can be employed to provide anoutput signal only when a preselected digital code is applied to therespective input terminals of the number filter. Thus. the number filterneed not take the specific form shown In FIG. 5 but can be of anysuitable design to provide an output signal only when uniquelyacitivatcd by the signals corresponding to the associated operand.

Continuing now with the description of the system shown in FIG. 2, thenumber filters 92-99 are identical in construction to filters 42-49 andinclude control input terminals l02-l09, respectively. for receivingsignals from output terminal 32' of number source 32. Number filters92-99 further include input terminals 112-119. respectively. commonlycoupled to the B+ supply voltage and output terminals 122-129, eachinterconnected to a plurality of associated correlator circuits. For theexample chosen (2'3 number source has its output terminal coupled tocorrelator 82 such that when number source 32 is actuated by the user ofthe system to provide an electrical signal corresponding to the number3. output terminal 125 will provide a positive output signal.

As seen in FIG. 2. in a system with a first and second operands. thecalculating system includes a correlators. one being assigned for eachunique pair of first and second number filters provided. In the figure.only three correlators for the operations on 22. 2-3 and 2-4 are shownfor the sake of clarity. it being understood that each number filter hasn correlators associated therewith. which correlators are coupled to then number filters of the other set.

The correlators can be constructed as shown in FIG. 6 where inputterminals 83 and 87 of correlator 82 are coupled to an AND gate 89having an output terminal 90 coupled to the input of an invertingamplifier 91 providing a second output terminal 90' from the correlator.When the two number filters associated with cor relator 82 in theexample are actuated by signals from number sources 30 and 32 associatedwith number filters 44 and 95. gate 89 will be actuated to provide apositive output signal (or a logic 1 output signal) at terminal 90 whileamplifier 9] responds to this signal to provide a logic 0 output signalat terminal 90'. In the present system. it is desired to provide both 1and O logic signals representing an operation to assure compatiblitywith existing logic systems which may be interfaced with the system. Insome systems. the inverting amplifier may not be required. Each of theremaining correlators is the same as shown in FIG. 2. In the embodimentshown. there will be 64 such correlators for the [6 number filters ofthe first and second series.

It is seen that each correlator. therefore. represents a unique solutionto the operation of one operand on a second operand. The outputconductors 90 and 90' of each correlator can be directly coupled to anoutput device which either displays in binary coded form the solution orprovides output signals of a format suitable for interface with othersystems. For the sake of simplicity. only the output wiring ofcorrelator 82 in FIG. 2 is shown and is interconnected to a displaypanel to provide a visual output indication of the resultant s0 lutionto the operations performed on the two operands.

Display I60 includes an array oflight emitting diodes 162 for providingan output indication for the operation of addition. an array 163 oflight emitting diodes providing an output indication of the operation ofsubtraction. an array 164 oflight emitting diodes providing the outputsolution to the operation of multiplication. and finally. an array 165of light emitting diodes providing the output solution for the operationof division. Each of the arrays of light emitting diodes includes aplurality of diodes sufficient to provide a unique display for thesolution for each and every operation associated with that array for theoperands of the system.

Extending from the output terminals of each correlator is a pair ofconductors (I70 and 172 for correlator 82) which are directly coupled topreselected ones of the diodes ofeach of the arrays such that when thecorrelator corresponding to two particular operands is actuated by theassociated number filters. the display 160 will provide a simultaneouslight output display in the preferred embodiment as illustrated by thewiring shown in FIG. 2.

Since a single array of light emitting diodes is used to display all ofthe solutions to the particular operation. it is seen that each lightemitting diode of the array will be electrically coupled to a pluralityof correlators in the computer system. It is necessary. therefore. toprovide current steering diodes to electrically isolate light emittingdiodes desired not to be actuated when the pair of conductors 170. I72from a correlator is actuated to activate the array.

Thus. for example. as seen on the multiplication operation of FIG. 2,where for the examples shown it is desired to actuate light emittingdiodes 162a and 16217 but not I620. a pair of steering diodes 166 and166' is provided such that diode I620 will not be actuated on theacutuation of conductors I70 and 172 but con versely will be actuatedupon the actuation of output conductors I73 and 174 from anothercorrelator corresponding to a different solution for one or moredifferent operators. The actuation of conductors I73 and 174 will.however, not actuate diodes 162a and 1621;. Similarly and in aconventional manner. current steering diodes will be provided forsuitably interconnecting the various output conductors I70 and 172 fromeach of the correlators to each of the arrays of the display I60.

It is seen that such a system lends itself to large scale integrationtechniques currently employed for manufacturing a plurality of solidstate devices on a single monolithic integrated circuit chip. Althoughin the computing system described herein. the actual circuit elementscan become somewhat expansive, the interconnection and the formation ofthe elements can be commercially achieved by virtue of the large scaleintegration techniques to make a practical working system.

For the example shown. it is seen that six light emitting diodes willprovide. for the functions add, subtract and multiply. the solution tothese operations for the selected operands. To provide the decimalinformation required for the division operation, in addition to the sixlight emitting diodes. a plurality of additional light emitting diodesI68 are provided together with decimal point indicators 167 to carry outthe division to the desired decimal point representation. Thus. forexample. output conductors I70 and 172 will be coupled. as seen in FIG.2. to the diodes as shown to provide the binary equivalent of the number66 with a decimal point preceding the binary equivalent to provide anoutput corresponding to 2+3 carried out to two decimal points. It isapparent that by adding additional diodes. the division can be carriedout to any desired number of digits.

In addition to the basic light emitting diodes of each array. the add.subtract and multiply arrays include a zero light emitting diode I6l foractivation when the solution to the operation is zero. A special lightemitting diode is provided for the subtract and divide operations toindicate a negative number and a nondivisible number respectively. Thesediodes are indicated as diodes I69 and 165' respectively.

By extending the structure describing the basic principle of operationherein to incorporate the desired number of operands. the system canaccommodate any degree of calculation desired on any number of operands.In addition. the system can be programmed to employ the basic principlesherein to provide mathematical operations other addition, conventionaladdition. subtraction. multiplication and division as noted earlier.Another embodiment of the invention which eliminates the usage ofeorrelators and. therefore, reduces the required number of circuitelements and computation time is shown in FIG. 7.

In the FIG. 7 circuit. there is provided a first number source 230having an output terminal 230' coupled to each of the control inputterminals 250-259 of a first series of number filters 240-249respectively. Each of the number filters includes signal input terminals260-269 which are coupled to a B+ voltage supply. shown in FIG. 7, suchthat at output terminals 270-279 associated with the number filters240-249. respectively. there will be applied an output signal only whenan electrical signal from source 230 corresponding to an operandactuates a particular number filter identifying the operand. In theexample shown in FIG. 7. the operand associated with source 230 is thenumber 6.

The output terminals of each of the number filters of the first set ofnumber filters are coupled to an additional series of number filtersidentical to those of the first series. Additional number filter series280-289, respectively. each include it number filters where n representsthe numbeer of different operands used in the system. The output voltageat the output terminals of the first series of number filters. whenpresent by the actuation of one of the filters of the first series.supplies the operating voltage for the voltage input terminals 360-369of the additional series (280-289) of number filters. The input controlsignal is provided by a second number source 232 having an outputterminal 232' coupled to each of the control input terminals of eachnumber filter in each additional series of number filters.

For the example shown in FIG. 7. the operand generated by the secondnumber source 232 is the number 5 which is applied to the input of theadditional series 286 of number filters associated with and coupled tooutput'terminal 276 of number filter 246 of the first series of numberfilters. Thus. when the first number source is actuated to generate anelectrical signal corresponding to the number 6 and the second numbersource is actuated to provide a signal representative of the number 5.only thefifth number filter 290 of the additional series 286 of numberfilters coupled to number filter 246 will be actuated to generate anoutput signal representative of the operations performed on operands 6and 5 in that order as indicated on the output conductor 292 associatedwith number filter 290.

There will be u number filters in the circuit shown in FIG. 7 with aunique number filter ofone ofthe additional series of number filtersbeing actuated upon the actuation of number sources 230 and 232. Each ofthe outputs of each number filter of each additional series of numberfilters will be coupled to arrays 300, 302, 304 and 306 of lightemitting diodes 308 which arrays can be identical to those shown in FIG.2 to provide an output display in binary coded form of the numericalequivalent of the operation performed. The display is not shown indetail in FIG. 7 since it is substantially identical to that shown inFIG. 2.

In the system shown in FIG. 7. therefore. only number filters areemployed together with the number sources to provide an activation of aunique output conductor corresponding to operations performed on a pairof operands. This signal provides a logic I signal used to actuate thedisplays in conjunction with a continuously generated logic developed bya low voltage (logic 0) generator 310 with an output terminal 3l2 whichis applied to the cathodes of the light emitting diodes in aconventional manner. Again. current steering diodes will be required toisolate the respective light emitting diodes to assure only thoseassociated with a unique conductor will be actuated to indicate the solution to the operation for the particular operands selected and appliedto the calculator.

It will become apparent to those skilled in the art that otherarrangements of number sources with number filters can be provided toprovide the parallel and simultaneous actuation of at least two numberfilters which in turn have their outputs uniquely coupled or combinedthrough circuit means or directly to activate an output circuit ordisplay for providing useful output information from the calculatorsystem. The embodiments shown in FIGS. 2 and 7 are illustrative of theprinciple in which the simultaneous parallel actuation of the numbersources greatly reduces the computing time of the system and permitsprogramming of a system for a particular operation or operations to beperformed on the operands inserted into the system.

The advantage of the system in addition to providing instantaneouscalculation is that a plurality of operations can be simultaneouslyoutputted and when this is combined with interface equipment, can beutilized to greatly increase the efficiency of a computer installationwhen. for example. the computing system described herein is employed asa subroutine to provide multiple and simultaneous outputs for differentoperations between two operands. Many modifications to the preferredembodiment can be made. for example. the number sources shown in H68. 2and 7 can be actuated by a keyboard and circuits as shown in FIG. 3.Alternatively. the number sources may themselves be incorporateddirectly in a keyboard with switches as shown in FIG. 4. These and othermodifications will, however. fall within the spirit and scope of thepresent invention as defined by the appended claims.

The embodiments of the invention in which an exclusive property orprivilege is claimed are defined as follows:

l. A calculating system for simultaneously performing and outputting thesolutions of multiple operations on two or more operands comprising:

number source means for generating multiple bit binary electricalsignals uniquely representing each number used in the system;

first number detector means coupled to said number source means forproviding a unique output signal identifying a first number whenactuated by a signal from said number source means representing saidfirst number;

second number detector means coupled to said number sou rec means forproviding a unique output signal identifying a second number whenactuated by a signal from said number source representing said secondnumber, wherein said first and second num ber detectors each comprisesat least one series of binary signal responsive circuits. each seriesincluding one circuit uniquely associated with each number of the systemand wherein each circuit includes a control terminal coupled to saidnumber source means and an output terminal providing an output signalthereat when a multiple bit binary electrical signal applied to saidcontrol terminal from said number source means corresponds to the numberuniquely identified by said circuit;

additional circuit means coupled to said first and second numberdetector means to provide an output signal uniquely identifying thecombination of first and second numbers entered into the system by saidnumber source means; and

output circuit means coupled to said additional circuit means andresponsive to signals therefrom to provide a simultaneous outputrepresentation of the solutions for two or more operations performed onnumbers entered into said system.

2. The system as defined in claim 1 wherein said number source meanscomprises first and second number sources having output terminalscoupled to each of said control terminals of said binary signalresponsive circuits associated only with said first and second binarysignal responsive number detectors, respectively. and actuatable togenerate signals uniquely identifying one of the numbers used in thesystem.

3. The system as defined in claim 2 wherein said additional circuitmeans comprises a series of logic circuits each having a first and asecond input terminal. one terminal of which is coupled to an outputterminal of a unique binary signal responsive circuit associated withsaid first number detector. the other terminal coupled to an outputterminal of a unique binary signal responsive circuit associated withsaid second number detector. said logic circuit including an outputterminal providing an output signal thereat only when predeterminedsignals are applied to said first and second input terminals of saidlogic circuit from the associated binary signal responsive circuits.

4. The system as defined in claim 3 wherein each of said logic circuitscomprises an AND gate and said series of logic circuits and AND gatescoupled to each unique pair of binary signal responsive circuits. oneAND gate being associated with each binary responsive signal circuit ofsaid first number detectors and a binary responsive signal circuitassociated with a predetermined one of said second number detectors.

5. The system as defined in claim 4 wherein said output circuit meanscomprises arrays of indicators coupled to said output terminal of eachof said AND gates to be actuated by a signal applied from an AND gate todisplay the solution to more than one operation performed between atleast two numbers generated by said number sources.

6. A calculating system for simultaneously performing and outputting thesolutions of multiple operations on two or more operands comprising:

means for generating electrical signals uniquely representing eachoperand used in the system;

first operand identification means coupled to said generating means forproviding a unique output signal identifying a first operand whenactuated by a signal from said generating means representing said firstoperand;

second operand identification means coupled to said generating means forproviding a unique output signal identifying a second operand whenactuated by a signal from said generating means representing said secondoperand; circuit means coupled to said first and second operandidentification means to provide an output signal uniquely identifyingthe combination of first and second operands entered into the system bysaid generating means wherein said first and second operandidentification means each comprises at least one series of detectorcircuits. each series including one detector uniquely associated witheach operand of the system and wherein each detector includes a controlterminal coupled to said generating means and an output terminalproviding an output signal thereat when an electrical signal applied tosaid control terminal from said generating means corresponds to theoperand uniquely identified by said detector and wherein said generatingmeans comprises first and second operand sources having output terminalscoupled to each of said control terminals of said detectors associatedonly with said first and second operand identifi cation means.respectively; and actuatable to generate signals uniquely identifyingone of the oper ands used in the system; said circuit means comprises aseries of AND circuits each having a first and a second input terminal.one terminal of which is coupled to an output terminal of a uniquedetector associated with said first operand identification means. theother terminal cou' pled to an output terminal of a unique detectorassociated with said second operand identification means said ANDcircuit including an output terminal providing an output signal thereatonly when signals are applied to said first and second input terminalsof said AND circuit from the associated detectors. wherein an ANDcircuits is provided and coupled to each unique pair of detectors. onedetector associated with said first operand identification means. theremaining detector associated with the second operand identificationmeans; and

output circuit means comprising a plurality of arrays ofindicators. eacharray coupled to said output terminals of said AND circuits tosimultaneously display the solutions to a plurality of operationsperformed between at least two operands generated by said operandsources.

7. A calculating system for simultaneously performing and outputting thesolutions of multiple operations on two or more operands comprising:

means for generating electrical signals uniquely representing eachoperand used in the system;

first operand identification means coupled to said generating means forproviding a unique output signal identifying a first operand whenactuated by a signal from said generating means representing said firstoperand;

second operand identification means coupled to said generating means forproviding a unique output signal identifying a second operand whenactuated by a signal from said generating means representing said secondoperand;

circuit means coupled to said first and second operand identificationmeans to provide an output signal uniquely identifying the combinationof first and second operands entered into the system by said generatingmeans;

output circuit means coupled to said circuit means and responsive tosignals therefrom to provide a simultaneous output representation of thesolutions for two or more operations performed on operands entered intosaid system. wherein said first operand identification means comprisesat least one series of detector circuits. said series including onedetector uniquely associated with each operand of the system and whereineach detector includes a control terminal coupled to said generatingmeans and an output terminal providing an output signal thereat when anelectrical signal applied to said control terminal from said generatingmeans corre sponds to the operand uniquely identified by said detectorcircuit; and

wherein said second operand identification means comprises a pluralityof series of detector circuits and said circuit means comprises meanscoupling input terminals of detector circuits of one series of each ofsaid plurality of series to an output terminal of a unique detectorassociated with said first operand identification means such that whensignals representing two operands are generated by said generatingmeans. a unique detector associated with said second operandidentification means will be actuated to provide a signal at an outputterminal thereof. said circuit means including additional means couplingoutput terminals of each detector of each series of said plurality ofseries of detectors other than said one series to said output circuitmeans.

8. The system as defined in claim 7 wherein said output circuit meanscomprises at least a first array of indi cators coupled to said outputterminals of each of said detectors of said operand identification meansto be actuated by a signal applied from a detector to display thesolution to an operation performed between at least two operandsgenerated by said generating means.

9. The system as defined in claim 8 wherein said output circuit meansincludes a plurality of arrays of indicators. each array coupled tooutput terminals of each of said detectors of said second operandidentification means to simultaneously display the solutions to aplurality of operations performed between at least two operandsgenerated by said generating means.

10. A system for providing high speed operations be tween two numberscomprising:

a first number source having an output terminal for providing electricalsignals thereat corresponding to any one of the numbers in the system;

a second number source having an output terminal for providingelectrical signals thereat corresponding to any number of the system;

a source of electrical potential.

at first series of number gates; each gate comprising an input terminalcoupled to said source of electrical potential. an output terminal. andat least one control terminal coupled to said output terminal of saidfirst number source. each of said gates including circuit meansresponsive to signals applied to said control terminal when anelectrical signal corresponding to the number assigned the particularnumber gate is applied to said control terminal from said first numbersource to couple a signal at said input terminal to said outputterminal:

a second series of number gates. each gate comprising an input terminalcoupled to said source of electrical potential an output terminal. andat least one control terminal coupled to said output terminal of saidsecond number source, each of said gates including circuit meansresponsive to signals applied to said control terminal when anelectrical signal corresponding to the number assigned the particularnumber gate is applied to said control terminal from said second numbersource to couple a signal at said input terminal to said output terminal;

a series of AND circuits coupling each combination of number gates ofsaid first and second series thereof, each AND circuit including a firstinput terminal coupled to one of said number gates of said first seriesof number gates and a second input terminal coupled to one of saidnumber gates of said second series of number gates for providing firstand second output signals at first and second output terminals thereofonly when both of the as sociated number gates are actuated by a numbersource to apply a signal to said AND circuit; and

means coupled to said first and second output terminals of said ANDcircuits to provide simultaneous output signals uniquely identifying theresultant numbers for more than one operation performed between numbersgenerated by said first and second number sources.

11. A system for providing high speed operations between two numberscomprising:

a first number source having an output terminal for providing electricalsignals thereat corresponding to numbers used in the system;

a second number source having an output terminal for providingelectrical signals thereat corresponding to numbers used in the system;

a source of electrical potential:

it first series of number detectors each comprisng individual circuitscorresponding to one of each of the numbers used in the system, saidcircuits having an input terminal coupled to said source ofelectricalpotential and an output terminal, said circuits including a controlterminal coupled to said output terminal of said first number source tobe actuated to apply a signal at said input terminal to said outputterminal of said detectors only when an electrical signal correspondingto the number assigned the detector is applied to said control terminalfrom said first number source; and at least a second series of numberdetectors comprising individual detector circuits corresponding to oneof each of the numbers used in the system, said circuits having an inputterminal coupled to an output terminal of one of said detectors of saidfirst se rites and each including an output terminal said circuitsincluding a control terminal coupled to said output terminal of saidsecond number source to be actuated to couple a signal applied to saidinput terminal from said detector of said first series to said outputterminals when an electrical signal corresponding to the number assignedsaid detector circuit in said second series is applied to said controlterminal from said second number source; and

output circuit means coupled to said output terminals of said secondseries of detectors to provide signals indicating the solution to anoperation performed between two numbers entered by said number sources.

[2. The system as defined in claim 11 and further including a pluralityof second series of number detectors with one series for each numberused in the system and each series including a detector for each numberused in the system; and means coupling input terminals of each detectorof a series of detectors to the output terminal of a unique detector ofsaid first series and the control input of each detector to said outputterminal of said second number source such that when said first numbersource provides a signal corresponding to a first number and said secondnumber source provides a signal corresponding to a number. only onenumber detector of said plurality of series of number detectors will beactuated to provide an output signal for the unique combination ofnumbers entered by said num ber sources.

1. A calculating system for simultaneously performing and outputting thesolutions of multiple operations on two or more operands comprising:number source means for generating multiple bit binary electricalsignals uniquely representing each number used in the system; firstnumber detector means coupled to said number source means for providinga unique output signal identifying a first number when actuated by asignal from said number source means representing said first number;second number detector means coupled to said number source means forproviding a unique output signal identifying a second number whenactuated by a signal from said number source representing said secondnumber, wherein said first and second number detectors each comprises atleast one series of binary signal responsive circuits, each seriesincluding one circuit uniquely associated with each number of the systemand wherein each circuit includes a control terminal coupled to saidnumber source means and an output terminal providing an output signalthereat when a multiple bit binary electrical signal applied to saidcontrol terminal from said number source means corresponds to the numberuniquely identified by said circuit; additional circuit means coupled tosaid first and second number detector means to provide an output signaluniquely identifying the combination of first and second numbers enteredinto the system by said number source means; and output circuit meanscoupled to said additional circuit means and responsive to signalstherefrom to provide a simultaneous output representation of thesolutions for two or more operations performed on numbers entered intosaid system.
 2. The system as defined in claim 1 wherein said numbersource means comprises first and second number sources having outputterminals coupled to each of said control terminals of said binarysignal responsive circuits associated only with said first and secondbinary signal responsive number detectors, respectively, and actuatableto generate signals uniquely identifying one of the numbers used in thesystem.
 3. The system as defined in claim 2 wherein said additionalcircuit means comprises a series of logic circuits each having a firstand a second input terminal, one terminal of which is coupled to anoutput terminal of a unique binary signal responsive circuit associatedwith said first number detector, the other terminal coupled to an outputterminal of a unique binary signal responsive circuit associated withsaid second number detector, said logic circuit including an outputterminal providing an output signal thereat only when predeterminedsignals are applied to said first and second input terminals of saidlogic circuit from the associated binary signal responsive circuits. 4.The system as defined in claim 3 wherein each of said logic circuitscomprises an AND gate and said series of logic circuits and AND gatescoupled to each unique pair of binary signal responsive ciRcuits, oneAND gate being associated with each binary responsive signal circuit ofsaid first number detectors and a binary responsive signal circuitassociated with a predetermined one of said second number detectors. 5.The system as defined in claim 4 wherein said output circuit meanscomprises arrays of indicators coupled to said output terminal of eachof said AND gates to be actuated by a signal applied from an AND gate todisplay the solution to more than one operation performed between atleast two numbers generated by said number sources.
 6. A calculatingsystem for simultaneously performing and outputting the solutions ofmultiple operations on two or more operands comprising: means forgenerating electrical signals uniquely representing each operand used inthe system; first operand identification means coupled to saidgenerating means for providing a unique output signal identifying afirst operand when actuated by a signal from said generating meansrepresenting said first operand; second operand identification meanscoupled to said generating means for providing a unique output signalidentifying a second operand when actuated by a signal from saidgenerating means representing said second operand; circuit means coupledto said first and second operand identification means to provide anoutput signal uniquely identifying the combination of first and secondoperands entered into the system by said generating means wherein saidfirst and second operand identification means each comprises at leastone series of detector circuits, each series including one detectoruniquely associated with each operand of the system and wherein eachdetector includes a control terminal coupled to said generating meansand an output terminal providing an output signal thereat when anelectrical signal applied to said control terminal from said generatingmeans corresponds to the operand uniquely identified by said detectorand wherein said generating means comprises first and second operandsources having output terminals coupled to each of said controlterminals of said detectors associated only with said first and secondoperand identification means, respectively, and actuatable to generatesignals uniquely identifying one of the operands used in the system;said circuit means comprises a series of AND circuits each having afirst and a second input terminal, one terminal of which is coupled toan output terminal of a unique detector associated with said firstoperand identification means, the other terminal coupled to an outputterminal of a unique detector associated with said second operandidentification means, said AND circuit including an output terminalproviding an output signal thereat only when signals are applied to saidfirst and second input terminals of said AND circuit from the associateddetectors, wherein an AND circuits is provided and coupled to eachunique pair of detectors, one detector associated with said firstoperand identification means, the remaining detector associated with thesecond operand identification means; and output circuit means comprisinga plurality of arrays of indicators, each array coupled to said outputterminals of said AND circuits to simultaneously display the solutionsto a plurality of operations performed between at least two operandsgenerated by said operand sources.
 7. A calculating system forsimultaneously performing and outputting the solutions of multipleoperations on two or more operands comprising: means for generatingelectrical signals uniquely representing each operand used in thesystem; first operand identification means coupled to said generatingmeans for providing a unique output signal identifying a first operandwhen actuated by a signal from said generating means representing saidfirst operand; second operand identification means coupled to saidgenerating means for providing a unique output signal identifying asecond operand when actuated by a signal from said generating meansrepresenting said second operand; circuit means coupled to said firstand second operand identification means to provide an output signaluniquely identifying the combination of first and second operandsentered into the system by said generating means; output circuit meanscoupled to said circuit means and responsive to signals therefrom toprovide a simultaneous output representation of the solutions for two ormore operations performed on operands entered into said system, whereinsaid first operand identification means comprises at least one series ofdetector circuits, said series including one detector uniquelyassociated with each operand of the system and wherein each detectorincludes a control terminal coupled to said generating means and anoutput terminal providing an output signal thereat when an electricalsignal applied to said control terminal from said generating meanscorresponds to the operand uniquely identified by said detector circuit;and wherein said second operand identification means comprises aplurality of series of detector circuits and said circuit meanscomprises means coupling input terminals of detector circuits of oneseries of each of said plurality of series to an output terminal of aunique detector associated with said first operand identification meanssuch that when signals representing two operands are generated by saidgenerating means, a unique detector associated with said second operandidentification means will be actuated to provide a signal at an outputterminal thereof, said circuit means including additional means couplingoutput terminals of each detector of each series of said plurality ofseries of detectors other than said one series to said output circuitmeans.
 8. The system as defined in claim 7 wherein said output circuitmeans comprises at least a first array of indicators coupled to saidoutput terminals of each of said detectors of said operandidentification means to be actuated by a signal applied from a detectorto display the solution to an operation performed between at least twooperands generated by said generating means.
 9. The system as defined inclaim 8 wherein said output circuit means includes a plurality of arraysof indicators, each array coupled to output terminals of each of saiddetectors of said second operand identification means to simultaneouslydisplay the solutions to a plurality of operations performed between atleast two operands generated by said generating means.
 10. A system forproviding high speed operations between two numbers comprising: a firstnumber source having an output terminal for providing electrical signalsthereat corresponding to any one of the numbers in the system; a secondnumber source having an output terminal for providing electrical signalsthereat corresponding to any number of the system; a source ofelectrical potential; a first series of number gates, each gatecomprising an input terminal coupled to said source of electricalpotential, an output terminal, and at least one control terminal coupledto said output terminal of said first number source, each of said gatesincluding circuit means responsive to signals applied to said controlterminal when an electrical signal corresponding to the number assignedthe particular number gate is applied to said control terminal from saidfirst number source to couple a signal at said input terminal to saidoutput terminal; a second series of number gates, each gate comprisingan input terminal coupled to said source of electrical potential, anoutput terminal, and at least one control terminal coupled to saidoutput terminal of said second number source, each of said gatesincluding circuit means responsive to signals applied to said controlterminal when an electrical signal corresponding to the number assignedthe particular number gate is applied to said control terminal from saidsecond number source to couple a signal at said input Terminal to saidoutput terminal; a series of AND circuits coupling each combination ofnumber gates of said first and second series thereof, each AND circuitincluding a first input terminal coupled to one of said number gates ofsaid first series of number gates and a second input terminal coupled toone of said number gates of said second series of number gates forproviding first and second output signals at first and second outputterminals thereof only when both of the associated number gates areactuated by a number source to apply a signal to said AND circuit; andmeans coupled to said first and second output terminals of said ANDcircuits to provide simultaneous output signals uniquely identifying theresultant numbers for more than one operation performed between numbersgenerated by said first and second number sources.
 11. A system forproviding high speed operations between two numbers comprising: a firstnumber source having an output terminal for providing electrical signalsthereat corresponding to numbers used in the system; a second numbersource having an output terminal for providing electrical signalsthereat corresponding to numbers used in the system; a source ofelectrical potential; a first series of number detectors each comprisngindividual circuits corresponding to one of each of the numbers used inthe system, said circuits having an input terminal coupled to saidsource of electrical potential and an output terminal, said circuitsincluding a control terminal coupled to said output terminal of saidfirst number source to be actuated to apply a signal at said inputterminal to said output terminal of said detectors only when anelectrical signal corresponding to the number assigned the detector isapplied to said control terminal from said first number source; and atleast a second series of number detectors comprising individual detectorcircuits corresponding to one of each of the numbers used in the system,said circuits having an input terminal coupled to an output terminal ofone of said detectors of said first series and each including an outputterminal, said circuits including a control terminal coupled to saidoutput terminal of said second number source to be actuated to couple asignal applied to said input terminal from said detector of said firstseries to said output terminals when an electrical signal correspondingto the number assigned said detector circuit in said second series isapplied to said control terminal from said second number source; andoutput circuit means coupled to said output terminals of said secondseries of detectors to provide signals indicating the solution to anoperation performed between two numbers entered by said number sources.12. The system as defined in claim 11 and further including a pluralityof second series of number detectors with one series for each numberused in the system and each series including a detector for each numberused in the system; and means coupling input terminals of each detectorof a series of detectors to the output terminal of a unique detector ofsaid first series and the control input of each detector to said outputterminal of said second number source such that when said first numbersource provides a signal corresponding to a first number and said secondnumber source provides a signal corresponding to a number, only onenumber detector of said plurality of series of number detectors will beactuated to provide an output signal for the unique combination ofnumbers entered by said number sources.